#    Makefile example
#    Bill French
#    August 9, 1999
#
#    This is a sample makefile 
#    Any line with a # is a comment

#  This is a macro to select which compiler you want to use.
CC = g++ -Wall
#  Anywhere where you see $(CC) it will be replaced with g++
#  This method is valuable because you can easily switch between 
#  compilers and add compiling options easily

#  The following will compile and link your program the format is:
#  target: dependancies
#  <tab>  command line 

#  if a target has a dependancy it must be placed higher in the file then
#  it's dependancy.

#  this target depends on sample.o and foo.o which are below
sample: sample.o foo.o
	$(CC) -o sample sample.o foo.o

sample.o: sample.cpp foo.h
	$(CC) -c sample.cpp

foo.o: foo.cpp foo.h
	$(CC) -c foo.cpp

#  it doesn't have to be a C++ command to be in the make file you
#  can put anything here.  The following would remove all the object 
#  files created during the make.
#  you can envoke this by typing make clean at the command line.
clean:
	rm *.o core sample