CSCI 620(380):  Computer Architecture

Registration/Schedule Information

This course is also being offered as a special session, self-paced, archived course. If you are interested in signing up for this course as a distance education student, please contact the Center for Regional and Continuing Education (RCE) by sending e-mail to rce@csuchico.edu, or call 530 898-6105 for detailed registration information.

Term/Year	TRACS   Call#	Section	Act	Days	Time	Room	Instructor
Spring 2005	11009	CSCI 380-01	DIS	MW	0400-0515	OCNL 119	Dr. J
Spring 2004	10985	CSCI 380-01	DIS	TR	1230-0145	OCNL 124	Dr. J

Prerequisites

CSCI 320 (CSCI 171), Computer Architecture; or
classified graduate-level status and permission of instructor.

Description

(3.0 credit units)  This graduate-level course focuses on advanced topics in the design and analysis of computer architectures. The course is designed to facilitate investigation of techniques of quantitative analysis and evaluation of modern computing systems, such as the selection of appropriate benchmarks to reveal and compare the performance of alternative design choices in system design. The emphasis is on the major component subsystems of high-performance computers: pipelining, instruction-level parallelism, memory hierarchies, storage systems, and network-oriented interconnections. Issues pertaining to architectural design of highly portable, power-limited computing systems will also be covered. Students will have an opportunity to conduct research in these and other related areas in the field of computer architecture.

(Outdated catalog description: Application of digital design techniques to the design of complete subsystems using a computer-aided design tool to simulate and verify correctness. Topics include the design of a three-port register file, hardware to multiply and divide, pipelining, and cache memory implementation.)

Class/Laboratory Schedule

• One hundred fifty minutes a week lecture (DIS)

Required Text

Computer Architecture: A Quantitative Approach, 4/e John L. Hennessy and David A. Patterson, 2006. Morgan Kaufmann/Elsevier Burlington, MA ISBN 978-0-12-370490-0 (Also available: Companion website to accompany the textbook.)

Recommended/Supplementary Material:

Computer Organization and Design, Revised Printing, 3/e David A. Patterson and John L. Hennessy, 2007. Morgan Kaufmann/Elsevier Burlington, MA ISBN 978-0-12-370606-5 (Also available: PDF lecture notes and companion website to accompany the textbook.)

Additional Requirements

	Students officially registered for the course will have their own Chico State Connection (CSC Portal) account.
	Students are responsible for regularly checking their WebCT account (automatically generated through the CSC Portal) to access an up-to-date on-line calendar of events, current scores, on-line quizzes, etc.
In addition to the required textbook indicated above, a reading list is available at http://www.ecst.csuchico.edu/~juliano/csci380/ReadingList.html. This list contains a list of relevant publications (available electronically) ordered by Chapter. A subset of the listed materials are required reading for the course.

Course Objectives

The objectives of this course are to:

1. introduce students to the main topics in computer architecture that address various aspects of concurrent computation;
2. foster an appreciation of architectural differences relative to a computer system's overall performance and capabilities/limitations in adapting to different applications; and
3. help students understand various representations and classifications of high performance architectures.

   
   

Course Outcomes

Upon successful completion of this course, the student shall be able to:

1. apply learned fundamental elements of computer architecture to address various aspects of concurrent computation;
2. understand and appreciate architectural differences relative to a computer system's overall performance and capabilities/limitations in adapting to different applications; and
3. clearly understand various representations and classifications of high performance architectures.

   
   

Grade Evaluation

This course will be conducted as a graduate seminar. The course is designed to give students an equal opportunity of exposure to both Theory and Practice. Students are expected to demonstrate proficiency on both the theoretical and practical aspects of this course.

Theoretical Component  (50%)
	40%		Midterm Exam
	60%		Final Exam (as scheduled in the Class Schedule)
Practical Component  (50%)
	100%		Written work
				* critique 3-5 papers from the Reading List
				* possible peer review/evaluation of individual work
				* possible written homework

Students are required to earn a C- (70%) or better in both the Theoretical and the Practical components; otherwise, the minimum of the scores of the two components will be used to calculate the student's final grade.

Final Grades

Final grades shall be expressed as a percentage of the maximum possible score of all evaluated materials. Letter grades will be given according to the following scheme:

Real Interval	Letter Grade	University Definition
[96.25,100.00]	A	Superior Work
[92.50, 96.25)	A-
[88.75, 92.50)	B+	Very Good Work
[85.00, 88.75)	B
[81.25, 85.00)	B-
[77.50, 81.25)	C+	Adequate Work
[73.75, 77.50)	C
[70.00, 73.75)	C-
N/A		Minimally Acceptable Work
[ 0, 70.00)	F	Unacceptable Work

Note:  It is Dr. J's policy not to assign a final grade of D or D+ to graduate students.

General Policies

Dr. J has some general policies that apply to all courses that he teaches. Students are expected to read and understand these policies upon registration of the course. What follows below are course-specific policies.

Written Homework

The professor reserves the right to grade only a subset of assigned homework. However, it is the student's responsibility to prepare for and participate in class discussions regarding all homework-related material. During class, students may be called at random to present lecture-related ideas and/or their own homework solutions. If a student is not present during any of these random selections, points will be deducted from that students' overall Homework score.

Tentative Schedule

The following tentative schedule is subject to change without notice:

Week	Chapter	Coverage/Comments
1	1	Introduction, background material
2	1 2	Performance; quantitative principles of computer design;     classifying instruction set architectures
3	2	Instruction set principles and examples
4	3	Instruction-level parallelism (ILP)
5	3	Hardware-based speculation;     thread-level parallelism (TLP)
6	4	Compiler support for ILP
7	4	Hardware and software speculation mechanisms      Midterm Exam, class time
8	5	Caches; main memory organization and technology
9	5	Virtual memory
10	6	Multiprocessors; models of memory consistency
11	6	Multithreading: TLP within a processor
12	7	Storage systems
13	7 8	Performance, queueing theory, and benchmarks;     interconnection networks
14	8	Interconnection networks and clusters
15		Catch-up and review
16		Final Exam, as scheduled (see Class Schedule)