CSCI 380:  Computer Architecture

READING LIST

This reading list is provided to supplement the material presented in the textbook. Please note that not all items listed are required reading; required reading are indicated by items with filled-in circles. Both the reading list and the subset of required reading are subject to change without notice. Please verify the currency of this list with the professor of instruction.

Chapter 1: Fundamentals of Computer Design

• M.J. Flynn, P. Hung, and K.W. Rudd, ``Deep-submicron microprocessor design issues,'' IEEE Micro, vol. 19, no. 4, pp. 11-22, July, 1999.
  
• M.J. Flynn, ``Basic issues in microprocessor architecture,'' Journal of Systems Architecture, vol. 45, no. 12-13, pp. 939-948, June, 1999.
  
• M.J. Flynn, ``Some reflections on computer engineering: 30 years after the IBM System 360 Model 91,'' invited talk, 30th Intl. Sym. on Microarchitecture, Durham, NC, December, 1997.
  
• M.J. Flynn, ``What's ahead in computer design?,'' in Proc. EuroMicro, pp. 4-9, September, 1997.
  
• P.P. Gelsinger et al., ``Microprocessors circa 2000,'' IEEE Spectrum, pp. 43-47, October, 1989.
  
• S. Hamilton, ``Semiconductor Research Corporation: Taking Moore's Law into the next century,'' IEEE Computer, vol. 32, no. 1, pp. 43-48, January, 1999.
  
• C.E. Kozyrakis and D.A. Patterson, ``A new direction for computer architecture research,'' IEEE Computer, vol. 31, no. 11, pp. 24-32, November, 1998.
  
• G.E. Moore, ``Cramming more components onto integrated circuits'' Electronics, vol. 38, no. 8, pp. 114-117, April, 1965.

  See also:

  • Intel's Silicon Showcase: Breaking Barriers to Moore's Law.
  • Interview (1997) by Scientific American.
  
  
• Y.N. Patt et al., ``One billion transistors, one uniprocessor, one chip'' IEEE Computer, vol. 30, no. 9, pp. 51-57, September, 1997.
  
• R. Ronen et al., ``Coming challenges in microarchitecture and architecture'' in Proc. IEEE, vol. 89, no. 3, pp. 325-340, March, 2001.
  
• M. Schlett, ``Trends in embedded-microprocessor design,'' IEEE Computer, vol. 31, no. 8, pp. 44-49, August, 1998.
  
• M. Slater, ``The microprocessor today,'' IEEE Micro, vol. 16, no. 6, pp. 32-44, December, 1996.
  
• J.E. Thornton, Considerations in Computer Design: Leading up to the Control Data 6600, Control Data Corporation, Chippewa, Illinois, 1963.
  

Chapter 2: Instruction Set Principles and Examples

• K. Diefendorff and others, ``Altivec Extension to PowerPC Accelerates Media Processing,'' IEEE Micro, vol. 20, no. 2, pp. 85-95, September, 2001.
• J. Fridman, and Z. Greenfield, ``The TigerSHARC DSP architecture,'' IEEE Micro, vol. 20, no. 1, pp. 66-76, January/February, 2000.
  
• M. Game and A. Booker, ``CodePack code compression for PowerPC processors,'' MicroNews, vol. 5, no. 1, 1999.
  
• T. Horel, and G. Lauterbach, ``UltraSPARC-III: Designing third-generation 64-bit performance,'' IEEE Micro, vol. 19, no. 3, pp. 73-86, May/June, 1999.
  
• J.  Huck et al., ``Introducing the IA-64 architecture,'' IEEE Micro, vol. 20, no. 5, pp. 12-23, September/October, 2000.
  
• A. Klaiber, ``The technology behind Crusoe$$TM processors,'' White paper, Transmeta Corporation, Santa Clara, California, January, 2000.
  
• P. Koopman, Stack Computers: The new wave, Mountain View Press, La Honda, CA, 1989.
• M. Mittal, A. Peleg and U. Weiser``MMX Technology Architecture Overivew,'' Intel Technology Journal, pp. 1-12, Q3, 1997.
• R.M. Russell, ``The CRAY-1 Computer System,'' Comm. of the ACM, vol. 21, no. 1, pp. 63-72, January, 1978.
  
• Sun Microsystems Inc., ``An overview of the UltraSPARC III Cu processor,'' White paper, Sun Microsystems, Inc., Palo Alto, California, June, 2002. (Adidtional information available from http://www.sun.com/processors/whitepapers/)
  
• E. Tam, ``A microarchitectural survey of next generation microprocessors,'' EECS 598.3 Term Project Report, The University of Michigan, April, 1995.
  
• Transmeta Corporation, `` Crusoe$$TM processor benchmark report,'' White paper, Transmeta Corporation, Santa Clara, California, January, 2000.
  
• E. Waingold et al., ``Baring it all to software: Raw machines,'' IEEE Computer, vol. 30, no. 9, pp. 86-93, September, 1997.
  

Chapter 3: Instruction-Level Parallelism and its Dynamic Exploitation

• J.D. Dundas, Improving Processor Performance by Dynamically Pre-Processing the Instruction Stream, Doctoral Dissertation, The University of Michigan, 1998.
  
• P.G. Emma, ``Branch prediction,'' Chapter 3 of D. Kaeli and P.-C. Yew (Eds), Speculative Execution in High Performance Computer Architectures, CRC Press, Boca Raton, FL, 2005.
• R. Espasa and M. Valero, ``Exploiting instruction- and data-level parallelism,'' IEEE Micro, vol. 17, no. 5, pp. 20-27, September/October, 1997.
  
• R. Espasa, M. Valero, and J.E. Smith, ``Vector architectures: Past, present and future,'' in Proc. Intl. Conf. on Supercomputing, pp. 425-432, 1998.
  
• S. Gopal et al., ``Speculative versioning cache,'' in Proc. 4th High-Performance Computer Architecture (HPCA), Febraury, 1998.
  
• S. McFarling, ``Combining branch predictors,'' Technical Report WRL TN-36, Western Research Laboratory, Digital Equipment Corporation, Palo Alto, California, June, 1993.
  
• A. Moshovos et al., ``Dynamic speculation and synchronization of data dependences,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), June, 1997.
  
• S.F. Oberman and M.J. Flynn, ``Design issues in division and other floating-point operations,'' IEEE Trans. Computers, vol. 46, no. 2, pp. 154-161, 1997.
  
• S.F. Oberman and M.J. Flynn, ``Division algorithms and implementations,'' IEEE Trans. Computers, vol. 46, no. 8, pp. 1833-854, 1997.
  
• M. Moudgill and S. Vassiliadisz, ``On precise interrupts,'' IEEE Micro, vol. 16, no. 1, pp. 58-67, January, 1996.
  
• B.R. Rau and J.A. Fisher, ``Instruction-level parallel processing: History, overview and perspective,'' Technical Report HPL-92-132, Computer Systems Laboratory, Hewlett Packard Laboratories, Palo Alto, California, October, 1992.
  
• A. Roth, A. Moshovos, and G.S. Sohi, ``Dependence based prefetching for linked data structures,'' in 8th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), October, 1998.
  
• K.W. Rudd, VLIW Processors: Efficiently Exploiting Instruction Level Parallelism, Doctoral Dissertation, Stanford University, December 1999.
  
• K.W. Rudd and M.J. Flynn, ``Instruction-level parallel processors: Dynamic and static scheduling tradeoffs,'' in Proc. IEEE Intl. Sym. on Parallel Algorithms Architecture Synthesis, March, 1997.
  
• A. Seznec et al., ``Design tradeoffs for the Alpha EV8 conditional branch predictor,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), May, 2002.
  
• J.E. Smith, ``Instruction Level Distributed Processing,'' in 7th Intl. Conf. on High Performance Computing (HiPC2000), December, 2000.
  
• J.E. Smith and A.R. Pleszkun, ``Implementing precise interrupts in pipelined processors,'' IEEE Trans. Computers, vol. 37, no. 5, pp. 562-573, May, 1988.
  
• J.E. Smith, ``A study of branch prediction strategies,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), pp. 135-148, May, 1981.
  
• J.E. Thornton, Design of a Computer: The Control Data 6600, Scott, Foresman and Company, Glenview, Illinois, 1970.
  
• R.M. Tomasulo, ``An efficient algorithm for exploiting multiple arithmetic units,'' IBM Journal of Research and Development, vol. 11, pp. 25-33, 1967.
  
• G. Uht, ``Multipath execution,'' Chapter 4 of D. Kaeli and P.-C. Yew (Eds), Speculative Execution in High Performance Computer Architectures, CRC Press, Boca Raton, FL, 2005.
• C. Young, N. Gloy, and M.D. Smith, ``A comparative analysis of schemes for correlated branch prediction,'' in Proc. Intl. Symposium on Computer Architecture (ISCA) June, 1995.
  

Chapter 4: Exploiting Instruction Level Parallelism with Software Approaches

• D. August, ``Branch predication,'' Chapter 5 of D. Kaeli and P.-C. Yew (Eds), Speculative Execution in High Performance Computer Architectures, CRC Press, Boca Raton, FL, 2005.
• T. Ball and J.R. Larus, ``Optimally profiling and tracing programs,'' ACM Trans. on Programming Languages and Systems, vol. 16, no. 4, pp. 1319-1360, July, 1994.
  
• J. Bharadwaj et al., ``The Intel IA-64 compiler code generator,'' IEEE Micro, vol. 20, no. 5, pp. 44-53, September/October, 2000.
  
• R.A. Bringmann, S.A. Mahlke, and W.W. Hwu, ``A study of the effects of compiler-controlled speculation on instruction and data caches,'' in Proc. 28th Annual Hawaii Intl. Conf. on System Sciences (HICSS), pp. 211-220, January, 1995.
  
• D. Bruening, S. Devabhaktuni, and S. Amarasinghe, ``Softspec: Software-based speculative parallelism,'' in Proc. 3rd ACM Workshop on Feedback-Directed and Dynamic Optimization (FDDO-3), December, 2000.
  
• P.P. Chang et al., ``Three architectural models for compiler-controlled speculative execution,'' IEEE Trans. Computers, vol. 44, no. 4, pp. 481-494, April, 1995.
  
• R.S. Chappell et al., ``Simultaneous subordinate microthreading (SSMT),'' in Proc. Intl. Symposium on Computer Architecture (ISCA), May, 1999.
  
• S.J. Eggers et al., ``Simultaneous multithreading: A platform for next-generation processors,'' IEEE Micro, vol. 17, no. 5, pp. 12-19, September/October, 1997.
  
• W.W. Hwu et al., ``The Superblock: An effective technique for VLIW and superscalar compilation,'' The Journal of Supercomputing, vol. 7, no. 1, pp. 229-248, January, 1993.
  
• D.A. Jimenez, and C. Lin, ``Neural methods for dynamic branch prediction,'' Technical Report TR-01-50, Department of Computer Science, The University of Texas at Austin, Austin, Texas, April, 2001.
  
• M. Liese, Explicitly parallel instruction computing, Masters' Project, California State University, Chico, 2002. (Abstract, TOC, Chapters 1, 2, 3, 4, 5, 6, 7, References, Appendix A, B)
  
• S.A. Mahlke, ``A comparison of full and partial predicated execution support for ILP processors,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), pp. 138-149, June, 1995.
  
• S.A. Mahlke et al., ``Sentinel scheduling for VLIW and superscalar processors,'' ACM SIGPLAN, vol. 27, no. 9, pp. 238-247, 1992.
  
• MC.. Merten et al., ``An Architectural Framework for Run-Time Optimization,'' IEEE Trans. Computers, vol. 50, no. 6, pp. 567-589, June, 2001.
  
• K. Skadron et al., ``Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques,'' IEEE Trans. Computers, vol. 48, no. 11, pp. 1260-1281, November, 1999.
  
• S. Palacharla, N.P. Jouppi and J.E. Smith, ``Complexity-effective superscalar processors,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), June, 1997.
  
• S. Papadimitriou, and T.C. Mowry, ``Exploring thread-level speculation in software: The effects of memory access tracking granularity,'' Technical Report CMU-CS-01-145, School of Computer Science, Carnegie Mellon University, Pittsburgh, Pennsylvania, July, 2001.
  
• M.S. Schlansker and B.R. Rau, ``EPIC: An architecture for instruction-level parallel processors,'' Technical Report HPL-1992-111, Compiler and Architecture Research, Hewlett Packard Laboratories, Palo Alto, California, October, 1992.
  
• H. Sharangpani and K. Arora, ``Itanium processor microarchitecture,'' IEEE Micro, vol. 20, no. 5, pp. 24-43, September/October, 2000.
  
• J.E. Smith and G.S. Sohi, ``The microarchitecture of superscalar processors,'' in Proc. IEEE, vol.  83, pp. 1609-1624, December, 1995.
  
• G.S. Sohi, S.E. Breach and T.N. Vijaykumar, ``Multiscalar processors,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), pp. 414-425, June, 1995.
  
• J.G. Steffan et al., ``Improving value communication for thread-level speculation ,'' in Proc. Intl. Symposium on High-Performance Computer Architecture (HPCA), February, 2002.
  
• D.M. Tullsen et al., ``Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), pp. 191-202, June, 1996.
  
• Y. Wu and J.R. Larus, ``Static branch frequency and program profile analysis,'' Technical Report CS-TR-1994-1248, University of Wisconsin-Madison, Madison, Wisconsin, 1994.
  
• P.-C. Yew, ``Compilation and speculation,'' Chapter 12 of D. Kaeli and P.-C. Yew (Eds), Speculative Execution in High Performance Computer Architectures, CRC Press, Boca Raton, FL, 2005.
• C. Zilles, J. Emer, and G.S. Sohi, ``The use of multithreading for software exception handling,'' in Proc. Intl. Symposium on Microarchitecture, November, 1999.
  

Chapter 5: Memory Hierarchy Design

• D.C. Burger, Hardware Techniques to Improve the Performance of the Processor/Memory Interface, Doctoral Dissertation, University of Wisconsin-Madison, 1998.
  
• D.C. Burger, J.R. Goodman, and G.S. Sohi, ``Memory Systems,'' in The Handbook of Computer Science and Engineering, CRC Press, 1997.
  
• B. Jacob and T.N. Mudge, ``Uniprocessor virtual memory without TLB,'' IEEE Trans. Computers, vol. 50, no. 5, pp. 482-499, May, 2001.
  
• B. Jacob and T.N. Mudge, ``Virtual memory in contemporary microprocessors,'' IEEE Micro, vol. 18, no. 4, July/August, 1998.
  
• B. Jacob and T.N. Mudge, ``Virtual memory: Issues of implementation,'' IEEE Computer, vol. 31, no. 6, June, 1998.
  
• C.E. Kozyrakis et al., ``Scalable processors in the billion-transistor era: IRAM,'' IEEE Computer, vol. 30, no. 9, pp. 75-78, September, 1997.
  
• H.-B. Lim and P.-C. Yew, ``Maintaining cache coherence through compiler-directed data prefetching,'' Journal of Parallel and Distributed Computing, vol. 53, no. 2, pp. 144-173, 1998.
  
• C.-K. Luk and T.C. Mowry, ``Automatic compiler-inserted prefetching for pointer-based applications,'' IEEE Trans. Computers, vol. 48, no. 2, pp. 134-141, 1999.
  
• T.C. Mowry, ``Tolerating latency in multiprocessors through compiler-inserted prefetching,'' ACM Trans. on Computer Systems, vol. 16, no. 1, pp. 55-92, February, 1998.
  
• P.J. Mucci and K. London, ``The CacheBench Report,'' CEWES MSRC/PET TR/98-25, March, 1998.
  
• F. Mueller, ``Timing analysis for instruction caches,'' Real-Time Systems, vol. 18, no. 2/3, pp. 209-239, May, 2000.
  
• F. Mueller, ``Generalizing timing predictions to set-associative caches,'' Technical Report, TR 96-66, Inst. f. Informatik, Humbolt University Berlin, July, 1996.
  
• O. Olukotun, T.N. Mudge and R.B. Brown, ``Multilevel optimization of pipelined caches,'' IEEE Trans. Computers, vol. 46, no. 10, pp. 1093-1102, October, 1997.
  
• S.J. Patel, D.H. Friendly, and Y.N. Patt, ``Evaluation of design options for the trace cache fetch mechanism,'' IEEE Trans. Computers, vol. 48, no. 2, pp. 193-204, February, 1999.
  
• D.A. Patterson et al., ``A case for Intelligent RAM,'' IEEE Micro, vol. 17, no. 2, pp. 34-44, March/April, 1997.
  
• G. Reinman, ``Instruction cache prefetching,'' Chapter 2 of D. Kaeli and P.-C. Yew (Eds), Speculative Execution in High Performance Computer Architectures, CRC Press, Boca Raton, FL, 2005.
• E. Rotenberg, ``Trace caches,'' Chapter 4 of D. Kaeli and P.-C. Yew (Eds), Speculative Execution in High Performance Computer Architectures, CRC Press, Boca Raton, FL, 2005.
• E. Rotenberg, S. Bennet, and J.E. Smith, ``A trace cache microarchitecture and evaluation,'' IEEE Trans. Computers, vol. 48, no. 2, pp. 111-120, February, 1999.
  
• E. Rotenberg, ``Trace processors: Exploiting hierarchy and speculation,'' IEEE Trans. Computers, vol. 48, no. 2, pp. 111-120, February, 1999.
  
• E. Rotenberg et al., ``Trace Processors,'' in Proc. Intl. Sym. on Microarchitecture, pp. 138-148, 1997.
  
• Y. Solihin and D. Leung, ``Data cache prefetching,'' Chapter 7 of D. Kaeli and P.-C. Yew (Eds), Speculative Execution in High Performance Computer Architectures, CRC Press, Boca Raton, FL, 2005.
• D.C. Winsor, Bus and Cache Memory Organizations for Multiprocessors, Doctoral Dissertation, The University of Michigan, 1989.
  

Chapter 6: Multiprocessors and Thread-Level Parallelism

• S.V.. Adve and K. Gharachorloo, ``Shared memory consistency models: A tutorial,'' IEEE Computer, vol. 29, no. 12, pp. 66-76, December, 1996.
  
• A. Agarwal, et al., ``Sparcle: An evolutionary processor design for large-scale multiprocessors,'' IEEE Micro, vol. 13, no. 3, pp. 48-61, March, 1993.
  
• A. Charlesworth, ``Starfire: Extending the SMP envelope,'' IEEE Micro, vol. 18, no. 1, pp. 39-49, January, 1998.
  
• M.J. Flynn and K.W. Rudd, ``Parallel Architectures,'' in ACM Computing Surveys, vol. 28, no. 1, pp. 67-70, March, 1996.
  
• C. Gniady, B. Falsafi, and T.N. Vijaykumar, ``Is SC + ILP = RC?,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), pp. 162-171, May, 1999.
  
• S. Kaxiras, ``Distributed vector architectures,'' Journal of Systems Architecture, vol. 46, no. 11, pp. 973-990, September, 2000.
  
• J.L. Lo et al., ``Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading,'' ACM Trans. on Computer Systems, vol. 15, no. 3, pp. 322-354, August, 1997.
  
• P. Marcuello, J. Sanchez, and A. Gonzalez, ``Multithreading and speculation,'' Chapter 13 of D. Kaeli and P.-C. Yew (Eds), Speculative Execution in High Performance Computer Architectures, CRC Press, Boca Raton, FL, 2005.
• D.A. Reed et al., ``Performance analysis of parallel systems: Approaches and open problems,'' in Proc. Joint Symp. Parallel Processing (JSPP), pp. 239-256, June, 1998.
  
• D.A. Wood and M.D. Hill, ``Cost-effective parallel computing,'' IEEE Computer, vol. 28, no. 2, pp. 69-72, February, 1995.
  

Chapter 7: Storage Systems

• J.H. Hartman, I. Murdoch, and T. Spalink, ``The Swarm scalable storage system,'' in Proc. Intl. Conf. on Distributed Computing Systems, pp. 74-81, 1999.
  
• K. Hwang, H. Jin, and R. Ho, ``RAID-x: A new distributed disk array for I/O-centric cluster computing,'' in Proc. Ninth IEEE Intl Symposium on High Performance Distributed Computing, pp. 279-287, IEEE Computer Society Press, Pittsburgh, Pennsylvania, 2001.
  
• R.H. Katz et al., ``RAID-II: Design and implementation of a large scale disk array controller,'' in Symposium on Integrated Systems (UCB/CSD 92/705), Berkeley, California, 1993.
  
• D.A. Patterson, G. Gibson, and R.H. Katz, ``A case for redundant arrays of inexpensive disks (RAID),'' in Proc. ACM SIGMOD Conference, Chicago, Illinois, pp. 109-116, June, 1988.
  
• R. Rabenseifner and A.E. Koniges, ``The effective I/O bandwidth benchmark (b_eff_io),'' in Proc. Message Passing Interface Developer's and User's Conference (MPIDC), 2000.
  
• H. Simitci and D.A. Reed, ``Adaptive disk striping for parallel I/O,'' in Proc. Seventh NASA Goddard Conference on Mass Storage Systems, San Diego, California, 1999.
  

Chapter 8: Interconnection Networks and Clusters

• S.V. Adve and K. Gharachorloo, ``Shared memory consistency models: A tutorial,'' IEEE Computer, vol. 29, no. 12, pp. 66-76, December, 1996.
  
• T.E. Anderson, D.E. Culler, and D.A. Patterson, ``A case for networks of workstations: NOW,'' IEEE Micro, vol. 15, no. 1, pp. 54-64, February, 1995.
  
• M. Baker, G.C. Fox, and H. Yau, ``Cluster computing review,'' Technical Report CRPC-TR95623, Center for Research on Parallel Computation, Rice University, Houston, Texas, November, 1995.
  
• M. Baker and G.C. Fox, ``Distributed cluster computing environments,'' 1996.
  
• L.A. Barroso et al., ``Piranha: A scalable architecture based on single-chip multiprocessing,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), pp. 282-293, June, 2000.
  
• R. Brightwell and S. Plimpton, ``Scalability and performance of two large Linux clusters,'' Journal of Parallel and Distributed Computing, vol. 61, no. 11, pp. 1546-1569, November, 2001.
  
• R. Brightwell et al., ``Massively parallel computing using commodity components,'' Parallel Computing, vol. 26, no. 2-3, pp. 243-266, 2000.
  
• A. Davis, M.R. Swanson, and M. Parker, ``Efficient communication mechanisms for cluster based parallel computing,'' in Proc. of Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC), pp. 1-15, December, 1996.
  
• J. Dinquel, ``Network architectures for cluster computing,'' report prepared for CECS 572 (Distributed Computing Systems and Networking), CSU Long Beach, April, 2000.
  
• I. Foster, C. Kesselman, and S. Tuecke, ``The anatomy of the Grid: Enabling scalable virtual organizations,'' in R. Sakellariou et al. (Eds.), Lecture Notes in Computer Science, vol. 2150, 2001.
  
• I. Foster and C. Kesselman, ``Computational Grids,'' Chapter 2 of The Grid: Blueprint for a New Computing Infrastructure, Morgan Kaufmann Publishers, 1999.
  
• G. Fox and D. Gannon, ``Computational Grids,'' IEEE Comput Sci & Eng, vol. 3, no. 4, pp. 74-77, July/August 2001.
  
• D. Gannon et al., ``Programming the Grid: Distributed software components, P2P and Grid web services for scientific applications,'' Journal on Cluster Computing, to appear, 2002.
  
• J. Laudon and D. Lenoski, ``The SGI Origin: A ccNUMA highly scalable server,'' in Proc. Intl. Symposium on Computer Architecture (ISCA), pp. 241-251, June, 1997.
  
• F. Petrini and M. Vanneschi, ``SMART: A simulator of massive architectures and topologies,'' 1997.
  
• C. Reschke et al., ``A design study of alternative network topologies for the Beowulf parallel workstation,'' in Proc. High Performance and Distributed Computing, pp. 626-636, 1996.
  
• D. Ridge et al., ``Beowulf: Harnessing the power of parallelism in a pile-of-PCs,'' in Proc. IEEE Aerospace, 1997.
  
• R. Riesen, R. Brightwell, and A.B. Maccabe, ``Differences between distributed and parallel systems,'' Technical Report SAND98-2221, Sandia National Laboratories, October, 1998.
  
• E. Rijpkema, K. Goossens, and P. Wielage, ``A router architecture for networks on silicon,'' in Proc. Progress 2001, 2nd Workshop on Embedded Systems, Veldhoven, the Netherlands, October, 2001.
  
• T. Sterling et al., ``Beowulf: A parallel workstation for scientific computation,'' in Proc. 24th Intl. Conf. Parallel Processing, Vol. 1, pp. 11-14, 1995.
  
• P. Wielage and K. Goossens, ``Networks on silicon: Blessing or nightmare?,'' in Proc. Euromicro Symposium on Digital System Design (DSD), Dortmund, Germany, September, 2002.
  

Appendix A: Pipelining - Basic and Intermediate Concepts

• University of Manchester, ``Asynchronous Logic Home Page,''; http://www.cs.man.ac.uk/async/ [current 27 Jan. 2003].
  
• Sun Microsystems Laboratories, ``Beating the Clock,''; Asynchronous Design Group, Sun Microsystems, Inc. http://research.sun.com/features/async/ [current 27 Jan. 2003].
  
• C. Tristram, ``It's Time for Clockless Chips,''; Technology Review, October, 2001 http://www.technologyreview.com/articles/tristram1001.asp [current 27 Jan. 2003].
  
• I.E. Sutherland and J. Ebergen, ``Computers without Clocks,''; Scientific American, August, 2002 http://www.sciam.com/article.cfm?articleID=00013F47-37CF-1D2A-97CA809EC588EEDF&pageNumber=1&catID=2 [current 27 Jan. 2003].
  
• G.H. Anthes, ``Computer Clocks Wind Down,''; Computerworld, December, 2002 http://www.computerworld.com/hardwaretopics/hardware/story/0,10801,76931,00.html [current 27 Jan. 2003].
  
• Technische Universiteit Eindhoven, ``The Asynchronous Bibliography,''; http://www.win.tue.nl/async-bib/ [current 27 Jan. 2003].
  

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