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CSCI 620: Computer Architecture
(3 credit hours)
Course Objectives
The objectives of this course are to:
- introduce students to the main topics in computer architecture that address various aspects of concurrent computation
- foster an appreciation of architectural differences relative to a computer system's overall performance and capabilities/limitations in adapting to different applications; and
- help students understand various representations and classifications of high performance architectures.
Prerequisites
Classified graduate standing, or faculty permission.
Catalog Description
Provides a thorough and fundamental treatment of the art of computer architecture. Topics include concepts of von Neumann architectures, methods of evaluating CPU performance, instruction-set design and examples, compiler issues, instruction pipelining, superscalar processors, methods for reduction of branch penalty, memory hierarchies, I/O systems, floating-point arithmetic, and current issues in parallel processing.
Approach
Study architecture by topics, using relevant portions of various real computers to illustrate each topic. Study implementation chiefly through the detailed examination of one simple, complete computer. Supplement the textbook with selected readings from the literature. Do not emphasize programming or hardware laboratory.
Current Instructor
Dr. Benjoe Juliano
Current Course Website
http://www.ecst.csuchico.edu/~juliano/Teaching/syllabus380.html
Typical Text
Computer Architecture: A Quantitative Approach, 3/e, John L. Hennessy and David A. Patterson, 2002. Morgan Kaufmann Publishers, San Francisco, California. ISBN 1-55860-596-7
Course Coverage
Basics of machine organization (review)
1. CPU
2. Datapath
3. Control: hardwired and microprogrammed
4. Memory
Principles of instruction set design
1. Instruction formats
2. Memory addressing
3. Types of instruction operators (including synchronization primitives, and their implementations on pipelined Load / Store machines)
4. Sizes of operands
5. How programs (and machines) behave--dynamic frequencies
Computer arithmetic
1. Fast add, multiply and divide units
2. Floating point arithmetic and the IEEE Floating Point Standard
Pipelining (instruction level parallelism)
1. Basics: notations, speedup, classification of pipelines
2. Instruction pipelining
- Hazards: structural, data and control hazards
- Hardware solutions: interlocks, forwarding, renaming, branch prediction
- Software solutions: pipeline scheduling, loop unrolling, loop-level parallelism
- Scoreboarding and Tomasulo's Algorithm
3. Out of order execution, speculative execution and precise interrupts
4. Multiple issue (superscalar and VLIW) processors
Memory hierarchy
1. Cache memory
- Addressing methods
- Fetch, write and replacement policies
- Split and unified caches
- Multilevel caches
- Physical and virtual caches
2. Virtual memory
- Methods of address translation
- Translation Lookaside Buffers
Multiprocessors
1. symmetric shared-memory versus distributed shared-memory architectures
2. cache coherence, bus-based or snoopy coherence protocols
3. scalability issues |
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