CSCI 380: Computer Architecture
(3 credit hours)
DRAFT, modified 15 April 2004

Develop an understanding of the architecture and implementation of modern desktop, server, and embedded processors. Understand the interdependence of architectural and implementation decisions through quantitative analysis and evaluation of modern computing systems, such as the selection of appropriate benchmarks to reveal and compare the performance of alternative design choices in system design.

Prerequisites

CSCI 171 (Computer Architecture)

Approach

Study architecture by topics, using relevant portions of various real computers to illustrate each topic. Study implementation chiefly through the detailed examination of one simple, complete computer. Supplement the textbook with selected readings from the literature. Do not emphasize programming or hardware laboratory.

Typical Text

John L. Hennessy and David A. Patterson, 2002.
Computer Architecture: A Quantitative Approach, 3/e.
Morgan Kaufmann Publishers, San Francisco, California.

Recommended Reference

David A. Patterson and John L. Hennessy, 2004.
Computer Organization and Design, 3/e.
Morgan Kaufmann Publishers, San Francisco, California.

Course Coverage

• Basics of machine organization (review)
  • CPU
  • Datapath
  • Control: hardwired and microprogrammed
  • Memory

• Principles of instruction set design
  • Instruction formats
  • Memory addressing
  • Types of instruction operators (including synchronization primitives, and their implementations on pipelined Load / Store machines)
  • Sizes of operands
  • How programs (and machines) behave--dynamic frequencies

• Computer arithmetic
  • Fast add, multiply and divide units
  • Floating point arithmetic and the IEEE Floating Point Standard

• Pipelining (instruction level parallelism)
  • Basics: notations, speedup, classification of pipelines
  • Instruction pipelining
    • Hazards: structural, data and control hazards
    • Hardware solutions: interlocks, forwarding, renaming, branch prediction
    • Software solutions: pipeline scheduling, loop unrolling, loop-level parallelism
    • Scoreboarding and Tomasulo's Algorithm
  • Out of order execution, speculative execution and precise interrupts
  • Multiple issue (superscalar and VLIW) processors

• Memory hierarchy
  • Cache memory
    • Addressing methods
    • Fetch, write and replacement policies
    • Split and unified caches
    • Multilevel caches
    • Physical and virtual caches
  • Virtual memory
    • Methods of address translation
    • Translation Lookaside Buffers

• Multiprocessors
  • symmetric shared-memory versus distributed shared-memory architectures
  • cache coherence, bus-based or snoopy coherence protocols
  • scalability issues

1. R. Espasa and M. Valero, ``Exploiting instruction- and data-level parallelism,'' IEEE Micro, vol. 17, no. 5, pp. 20-27, September/October, 1997.
2. M.J. Flynn, ``Basic issues in microprocessor architecture,'' Journal of Systems Architecture, vol. 45, no. 12-13, pp. 939-948, June, 1999.
3. B. Jacob and T.N. Mudge, ``Virtual memory in contemporary microprocessors,'' IEEE Micro, vol. 18, no. 4, July/August, 1998.
4. G.E. Moore, ``Cramming more components onto integrated circuits'' Electronics, vol. 38, no. 8, pp. 114-117, April, 1965.
5. S.F. Oberman and M.J. Flynn, ``Division algorithms and implementations,'' IEEE Trans. Computers, vol. 46, no. 8, pp. 1833-854, 1997.
6. J.E. Smith and A.R. Pleszkun, ``Implementing precise interrupts in pipelined processors,'' IEEE Trans. Computers, vol. 37, no. 5, pp. 562-573, May, 1988.